The present invention relates to a burst order control circuit and a method thereof for controlling a burst order in a semiconductor device.
The semiconductor device determines a burst order (data output sequence) based on a seed column address. A circuit for controlling this is referred to as a burst order control circuit.
FIG. 1 is a conventional burst order control circuit.
As shown in FIG. 1, the conventional burst order control circuit includes a burst signal generating unit 110, a repeater unit 120 and a pipe latch 130.
The burst signal generation unit 110 receives a seed column address A<0:2>, a read command signal CASP12RD and latency signals LATENCYSSB and LATENCY2, and generates a burst signal SOSEB<0:2> in response to the read command signal CASP12RD.
A logic level of the burst signal SOSEB<0:2> is identical to a logic level of the seed column address A<0:2>. A first burst signal SOSEB<1> starts the logic value of the seed column address A<1> as an initial value and is toggled at every clock cycle. A second burst signal SOSEB<2> starts the logic value of the seed column address A<2> and is toggled at every other clock cycle.
The latency signals LATENCYSSB and LATENCY2 inputted to the burst signal generating unit 110 have timing information. A first latency signal LATENCYSSB is activated three clock cycles prior to an output clock of data (CL-3). A second latency signal LATENCY2 is activated two clock cycles prior to the output clock of data (CL-2).
The read command signal CASP12RD is activated when a read command CASP12RD is applied.
The burst signal generating unit 110 receives the seed column address A<0:2> in response to the read command signal CASP12RD. The burst signal generating unit 110 adjusts, toggles and transfers a timing of the burst signal SOSEB<0:2> to the repeater unit 120 based on the latency signals LATENCYSSB and LATENCY2.
The repeater unit 120 generates a rising burst signal SOSEBR<1:2> and a falling burst signal SOSEBF<1:2> in response to the burst signal SOSEB<0:2>. The repeater unit 120 shifts the rising burst signal SOSEBR<1:2> and the falling burst signal SOSEBF<1:2> to a data output clock (CL-0), and transfers the rising burst signal SOSEBR<1:2> and the falling burst signal SOSEBF<1:2> to the pipe latch 130.
Logic levels of a second rising burst signal SOSEBR<2> and a second falling burst signal SOSEBF<2> are identical to a logic level of the second burst signal SOSEB<2>. A first rising burst signal SOSEBR<1> has the same logic level as the first burst signal SOSEB<1>. However, a first falling burst signal SOSEBF<1> may have the same logic level as the first burst signal SOSEB<1> or an inverse logic level to the first burst signal SOSEB<1>.
Whether the first falling burst signal SOSEBF<1> has the same logic level as the first burst signal SOSEB<1> or not is determined based on a logic level of a zero burst signal SOSEB<0> and a burst mode setting signal SEQBINT as shown in FIG. 2.
The rising burst signal SOSEBR<1:2> outputted from the repeater unit 120 is transferred to the pipe latch 130, is aligned at a rising clock RCLKDLL and determines a burst order of data to be outputted. The falling burst signal SOSEBF<1:2> outputted from the repeater unit 120 is transferred to the pipe latch 130, is aligned at a falling clock FCLKDLL and determines a burst order of data to be outputted.
For reference, control signals such as the burst signal SOSEB<0:2>, the rising burst signal SOSEBR<1:2> and the falling burst signal SOSEBF<1:2> are toggled at every period and have a different logic value at every clock cycle. Because <1> denotes a toggle at every clock period, <2> denotes a toggle at every other clock period, <1:2> has the same logic value at every four clock cycles.
FIG. 2 is a detailed block diagram illustrating the repeater unit shown in FIG. 1.
As shown in FIG. 2, the repeater unit includes a first shifter unit 210, a second shifter unit 220, a third shifter unit 230, a fourth shifter unit 240, a control signal selection unit 250 and a fifth shifter unit 260.
The first shifter unit 210 receives the second burst signal SOSEB<2> and the falling clock FCLKDLL. The first shifter unit 210 shifts the second burst signal SOSEB<2> for a period of one clock cycle and outputs the second rising burst signal SOSEBR<2> in response to the falling clock FCLKDLL.
The second shifter unit 220 receives the second rising burst signal SOSEBR<2> and the rising clock RCLKDLL. The second shifter unit 220 shifts the second rising burst signal SOSEBR<2> for a period of a half clock cycle and outputs the second falling burst signal SOSEBF<2> in response to the rising clock RCLKDLL. The second rising burst signal SOSEBR<2> determines a burst order of rising data, and the second falling burst signal SOSEBF<2> determines a burst order of falling data. The second rising burst signal SOSEBR<2> has a timing difference of a half clock period from the second falling burst signal SOSEBF<2>.
The third shifter unit 230 receives the first burst signal SOSEB<1> and the falling clock FCLKDLL. The third shifter unit 230 shifts the first burst signal for a period of one clock cycle and outputs the first rising burst signal SOSEBR<1> in response to the falling clock FCLKDLL.
The fourth shifter unit 240 receives the zero burst signal SOSEB<0> and the falling clock FCLKDLL. The fourth shifter unit 240 shifts the zero burst signal SOSEB<0> for a period of one clock cycle and outputs the zero burst signal SOSEB<0> shifted in response to the falling clock FCLKDLL.
The control signal selection unit 250 receives the zero burst signal SOSEB<0> shifted, the first rising burst signal SOSEBR<1> and the burst mode setting signal SEQBINT. The control signal selection unit 250 inverts or does not invert the first rising burst signal SOSEBR<1> in response to the burst mode setting signal SEQBINT and the zero burst signal SOSEB<0>.
The fifth shifter unit 260 receives an output of the control signal selection unit 250 and the rising clock RCLKDLL. The fifth shifter unit 260 shifts the output of the control signal selection unit 250 for a period of a half clock cycle and outputs the first falling burst signal SOSEBF<1> in response to the rising clock RCLKDLL.
FIG. 3 is a timing diagram illustrating a conventional burst order control circuit.
Referring to FIGS. 1 to 3, the burst signal SOSEB<1:2> is outputted from the burst signal generating unit 110 while the burst control signal is activated at one and a half clock prior to the output clock of data (CL-1.5).
The repeater unit 120 shifts the burst signal SOSEB<1:2> for a period of one clock cycle and generates the rising burst signal SOSEBR<1:2>. The repeater unit 120 generates the falling burst signal SOSEBF<1:2> using the rising burst signal SOSEBR<1:2>, and shifts and outputs the falling burst signal SOSEBF<1:2> for a period of a half clock cycle.
A logic value of the first rising burst signal SOSEBR<1> or the first falling burst signal SOSEBF<1> is determined by a logic value of the zero burst signal SOSEB<0> and the burst mode setting signal SEQBINT.
The repeater unit 210 generates the first rising burst signal SOSEBR<1> and the first falling burst signal SOSEBF<1> shifted for a period of a half clock cycle. Because the operation of the repeater unit 210 is to be completed within a half clock cycle, the operation of the repeater may be unstable.
Because the falling burst signal SOSEBF<1:2> is generated from the second and fifth shifter units 220 and 250 which receive the rising burst signal SOSEBR<1:2>, an output node of the rising burst signal SOSEBR<1:2> has a loading difference from an output node of the falling burst signal SOSEBF<1:2>, and a duty characteristic and a skew of the rising burst signal SOSEBR<1:2> and the falling burst signal SOSEBF<1:2> deteriorate. That is, because of the shortage of an operation margin, an operation of the burst order control circuit is unstable.